The present invention relates generally to demodulators for communications equipment and, in particular, to demodulators for phase-shift-keyed or analogous communications signals.
Phase-shift-keying (PSK) demodulators often have used inflexible fixed-function circuitry limited to particular applications. Consequently, new or different applications have required designing new circuitry for particular applications, which tended to increase costs of the demodulators.
Application Specific Integrated Circuits (ASIC""s) and phase locked loops (PLL""s) are illustrative examples of fixed-function circuitry used in PSK demodulators. An ASIC may comprise a dedicated algorithm to recover the message content of a received signal. Similarly, a PLL comprises an oscillator control mechanism that limits the practical frequency range of demodulators. While the frequency range of a PLL circuit may be enhanced by using adjustable components or replacing components, such hardware changes may require disassembly of the PLL circuit, its housing, or other disruptive measures. Thus, a need exists for a cost-effective demodulator that is readily apposite to a wide assortment of applications.
One problem with certain existing demodulators is insufficient immunity to spurious noise. Noise may be caused by a prodigious variety of man-made sources that intentionally or unintentionally radiate electromagnetic energy within a frequency range affecting a PSK carrier frequency of interest. Typical sources of noise include telecommunications equipment, electric motors, generators, and internal combustion engines, among others. As referred to herein, inter-message noise refers to electromagnetic noise energy between PSK messages. Inter-message noise may be modeled as a randomly occurring electromagnetic signal with an amplitude characterized by a probability density function. Inter-message noise tends to degrade reception of PSK messages and interpretation of demodulated data. A demodulator with insufficient immunity to noise is characterized by an unacceptably high frequency of false phase shift detections. To increase immunity to noise, some electronic manufacturers have attenuated the received signal at the PSK demodulator. However, an unwanted side effect of such attenuation is reduced sensitivity of the demodulator, which may make weaker received signals incapable of being properly detected. Thus, a need exists for a demodulator which has suitable immunity to noise without unduly sacrificing sensitivity. A need also exists for a demodulator with minimal attenuation levels suitable for obtaining received signal strength indicator (RSSI) measurements over the broadest possible range at the demodulator.
In accordance with the invention, a demodulator reduces or eliminates inter-message noise which would otherwise degrade the reception or interpretation of demodulated data. The demodulator reduces or eliminates noise based upon a period-width windowing evaluation of a communications signal to accurately time the presence of a message interval and to disable a demodulator output outside of the message interval. The period-width windowing evaluation identifies phase shifts in the communications signal as deviations from an adjustable time window, called a period-width window. The period-width window is readily adjustable to accommodate different carrier frequencies because the demodulator is well-suited for fabrication using programmable digital logic circuitry.
The demodulator may be readily incorporated into receivers or transceivers to reduce or eliminate inter-message noise. In addition, the demodulator contributes toward maximizing receive sensitivity of its host receiver by eliminating the potential need for an attenuator to reduce noise at the receiver. Consequently, the demodulator is well-suited for operation in tandem with a receive signal strength indicator to measure a broad dynamic range of signal strengths.
In accordance with the invention, a demodulator for demodulating a PSK communications signal synchronizes the demodulator with the communication signal by generating a transition signal modulated to represent reference edges of the communication signal. The demodulator measures a time interval between the reference edges of the communications signal and establishes a durational state associated with the measured time interval. The durational state is used to logically derive a logic output signal indicating the presence or absence of a phase shift in the communications signal.
The communications signal preferably includes a phase-shift modulated state and a generally unmodulated carrier state. The demodulator is adapted to detect the state of the communications signal and control the enablement of the demodulator output based upon whether the communications signal is in the phase-shift modulated state or the unmodulated state. Appropriately controlling the enablement of the demodulator reduces or eliminates noise reception of inter-message noise.
The demodulator of the invention is preferably manufactured by using only minimal discrete components and basic printed circuit board (PCB) fabrication techniques. The demodulator is readily implemented with flexible architecture, known as a field programmable gate array (FPGA) technology. An FPGA-based demodulator may have a lower production cost than fixed-function demodulators if the FPGA demodulator is suited to a sufficiently large common pool of applications to meet manufacturing target volumes. For example, an FPGA demodulator may be programmed to account for drift of a carrier frequency or a different carrier frequency to maximize production volume; hence, reduce production costs.